Principal Verification Engineer

Astera Labs · San Jose, California, United States · More jobs in San Jose · United States

Design & UX · Lead / manager

Published by the employer 2026-09-29 · Last observed 2026-10-13

About the role

Design Verification CCE2 · San Jose, California, United States Full requirements and the application form are on the employer's original listing.

Teach Lead Physical Design Engineer · Astera Labs · Singapore, Singapore
Principal Physical Design Engineer · Astera Labs · Singapore, Singapore
Analog Mixed Signal Design Engineer · Astera Labs · Singapore, Singapore
Tech Lead Analog Mixed-Signal IC Layout Engineer · Astera Labs · Singapore, Singapore
Senior Analog Mixed-Signal IC Layout Engineer · Astera Labs · Singapore, Singapore
Senior Manager, Global Safety & Security · Astera Labs · San Jose, California, United States